Chip-stack structure

ABSTRACT

The present disclosure provides a manufacturing method of a die-stack structure including follow steps. A first wafer including a first die is provided, wherein the first die includes a first substrate material layer, a first interconnect structure, and a first pad, and the first interconnect structure and the first pad are formed on the first substrate material layer in order, and the first substrate material layer has a first contact conductor disposed therein. a first contact conductor is disposed in the first substrate material layer. A second wafer including a second die is provided, wherein the second die includes a second substrate material layer, a second interconnect structure, and a second pad, and the second interconnect structure and the second pad are formed on the second substrate material layer in order, and the second substrate material layer has a second contact conductor disposed therein. A portion of the first substrate material layer is removed to form a first substrate, wherein the first contact conductor is exposed to a surface of the first substrate away from the first interconnect structure. The second wafer is covered on the first substrate such that the first contact conductor is directly physically in contact with the second pad.

CROSS REFERENCE TO RELATED APPLICATION

This application is a continuation application of and claims thepriority benefit of U.S. application Ser. No. 16/402,058, filed on May2, 2019, now pending. The prior U.S. application Ser. No. 16/402,058 isa divisional application of and claims the priority benefit of U.S.application Ser. No. 15/673,223, filed on Aug. 9, 2017, now patented,which claims the priority benefit of China application serial no.201710600400.X, filed on Jul. 21, 2017. The entirety of each of theabove-mentioned patent applications is hereby incorporated by referenceherein and made a part of specification.

BACKGROUND OF THE INVENTION Field of the Invention

The invention relates to a semiconductor structure and a manufacturingmethod thereof, and more particularly, to a chip-stack structure and amanufacturing method of a die-stack structure.

Description of Related Art

With the advancement of electronic manufacturing techniques, more andmore electronic products are developed to be portable, highlyfunctional, and compact and lightweight, such that the functionality ofthe chips used in conjunction and the electronic devices thereof arealso bound to be more numerous and complex. Under this requirement, thedesign of a three-dimensional integrated circuit (3D IC) is becomingpopular.

However, 3D IC not only faces relevant technical issues such as waferthinning and chip stacking, the front-end and back-end processes of theIC also have issues hidden in manufacture details, and the high cost andlow production yield thereof are the main issues of this technology.Therefore, how to reduce the production cost of 3D IC and increase theprocess yield thereof is an important topic for those skilled in theart.

SUMMARY OF THE INVENTION

The invention provides a chip-stack structure and a manufacturing methodof a die-stack structure having a simple process and high process yield.

An embodiment of the invention provides a chip-stack structure includinga first chip and a second chip. The second chip is located on the firstchip. The first chip includes a first substrate, a first interconnectstructure, a first pad, and a first contact conductor. The firstinterconnect structure is located on a first surface of the firstsubstrate. The first pad is located on the first interconnect structure.The first contact conductor is located in the first substrate andexposed on a second surface of the first substrate opposite to the firstsurface. The second chip includes a second substrate, a secondinterconnect structure, a second pad, and a second contact conductor.The second interconnect structure is located on the second substrate.The second pad is located on the second interconnect structure. Thesecond contact conductor is located in the second substrate, wherein thefirst contact conductor is directly physically in contact with thesecond pad.

In an embodiment of the invention, the first contact conductor does notcover the second surface of the first substrate.

In an embodiment of the invention, a carrier plate located below thefirst chip is further included.

In an embodiment of the invention, the carrier plate includes a carrierchip, and the first pad of the first chip is connected to a pad of thecarrier chip.

In an embodiment of the invention, the thickness of the carrier chip isgreater than the thickness of the first chip.

In an embodiment of the invention, a dielectric layer located betweenthe first chip and the second chip is further included.

In an embodiment of the invention, the active surface of the second chipfaces the back of the first chip.

Another embodiment of the invention provides a chip-stack structureincluding a first chip and a second chip. The second chip is located onthe first chip. The first chip includes a first substrate, a firstinterconnect structure, a first pad, and a first contact conductor. Thefirst interconnect structure is located on a first surface of the firstsubstrate. The first pad is located on the first interconnect structure.The first contact conductor is located in the first substrate andexposed on a second surface of the first substrate opposite to the firstsurface. The second chip includes a second substrate, a secondinterconnect structure, a second pad, and a second contact conductor.The second interconnect structure is located on the second substrate.The second pad is located on the second interconnect structure. Thesecond contact conductor is located in the second substrate, wherein thefirst contact conductor is directly physically in contact with thesecond pad, the first contact conductor has a width A, the second padhas a width B, and 5≤B/A.

In an embodiment of the invention, the first contact conductor does notcover the second surface of the first substrate.

In an embodiment of the invention, a carrier plate located below thefirst chip is further included.

In an embodiment of the invention, the carrier plate includes a carrierchip, and the first pad of the first chip is connected to a pad of thecarrier chip.

In an embodiment of the invention, the thickness of the carrier chip isgreater than the thickness of the first chip.

In an embodiment of the invention, a dielectric layer located betweenthe first chip and the second chip is further included.

In an embodiment of the invention, the active surface of the second chipfaces the back of the first chip.

An embodiment of the invention provides a manufacturing method of adie-stack structure including the following steps. A first waferincluding a first die is provided, wherein the first die includes afirst substrate material layer and a first interconnect structure and afirst pad formed on the first substrate material layer in order, and thefirst substrate material has a first contact conductor disposed therein.A second wafer including a second die is provided, wherein the seconddie includes a second substrate material layer and a second interconnectstructure and a second pad formed on the second substrate material layerin order, and the second substrate material has a second contactconductor disposed therein. A portion of the first substrate materiallayer is removed to form a first substrate, and the first contactconductor is exposed to the surface of the first substrate away from thefirst interconnect structure. The second wafer is covered on the firstsubstrate such that the first contact conductor is directly physicallyin contact with the second pad.

In an embodiment of the invention, the first contact conductor does notcover the surface of the first substrate away from the firstinterconnect structure.

In an embodiment of the invention, before a portion of the firstsubstrate material layer is removed, the first wafer is further disposedon the carrier plate.

In an embodiment of the invention, the carrier plate includes a carrierwafer, and the carrier wafer includes a third die, wherein the first padof the first die is connected to a pad of the third die.

In an embodiment of the invention, the active surface of the second diefaces the back of the first die.

In an embodiment of the invention, after a portion of the firstsubstrate material layer is removed, a dielectric layer is furtherformed on the surface of the first substrate away from the firstinterconnect structure, wherein the dielectric layer exposes the firstcontact conductor.

Based on the above, in the chip-stack structure and the manufacturingmethod of the die-stack structure provided in the embodiments of theinvention, since the first contact conductor is directly physically incontact with the second pad, a pad for connecting the first contactconductor and the second pad does not need to be formed on the secondsurface of the first substrate, such that the process can be simplified,and the process yield of the chip-stack structure can be increased andproduction cost thereof can be reduced.

In order to make the aforementioned features and advantages of thedisclosure more comprehensible, embodiments accompanied with figures aredescribed in detail below.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention.

FIG. 1A to FIG. 1E are cross sections of a manufacturing method of adie-stack structure according to an embodiment of the invention.

FIG. 2 is a cross section of a die-stack structure according to anotherembodiment of the invention.

FIG. 3 is a cross section of a chip-stack structure according to anotherembodiment of the invention.

DESCRIPTION OF THE EMBODIMENTS

The invention is more comprehensively described with reference to thefigures of the present embodiments. However, the invention can also beimplemented in various different forms, and is not limited to theembodiments in the present specification. The thicknesses of the layersand regions in the figures are enlarged for clarity. The same or similarreference numerals represent the same or similar devices and are notrepeated in the following paragraphs.

FIG. 1A to FIG. 1E are cross sections of a manufacturing method of adie-stack structure according to an embodiment of the invention. FIG. 2is a cross section of a die-stack structure according to anotherembodiment of the invention. FIG. 3 is a cross section of a chip-stackstructure according to another embodiment of the invention.

Referring to FIG. 1A, a wafer 100 is provided. The wafer 100 includes aplurality of dies, and FIG. 1A only shows one of the dies 101 (i.e.,first die). The die 101 includes a substrate material layer 102, aninterconnect structure 108, a pad 110, a contact conductor 112, and adielectric layer 114. The substrate material layer 102 includes asemiconductor substrate. The semiconductor substrate is, for instance, adoped silicon substrate, an undoped silicon substrate, or asilicon-on-insulator (SOI) substrate. The doped silicon substrate can beP-type doped, N-type doped, or a combination thereof. In someembodiments, an active device such as a charge-coupled device (CCD),P-type metal-oxide-semiconductor (PMOS) transistor, N-typemetal-oxide-semiconductor (NMOS) transistor, complementarymetal-oxide-semiconductor (CMOS) transistor, photodiode, or acombination thereof can be disposed in and/or on the substrate materiallayer 102. A passive device such as a capacitor, resistor, inductor, ora combination can also be disposed on the substrate material layer 102.In some embodiments, the substrate material layer 102 further includesan inter-layer dielectric, (ILD) and/or a contact, but the invention isnot limited thereto.

The interconnect structure 108 is formed on the substrate material layer102. The interconnect structure 108 includes a dielectric layer 104 anda plurality of wires 106 formed in the dielectric layer 104. Thedielectric layer 104 is, for instance, an inter-metal dielectric (IMD)layer, and the material thereof can be a dielectric material. Forinstance, the dielectric material can be silicon oxide,tetraethoxysilane (TEOS) silicon oxide, silicon nitride, siliconoxynitride, undoped silica glass (USG), borophosphosilicate glass(BPSG), phosphosilicate glass (PSG), a low-k material having adielectric constant less than 4, or a combination thereof. The low-kmaterial is, for instance, fluorosilicate glass (FSG), silsesquioxnane,aromatic hydrocarbon, organosilicate glass, parylene, fluoro-polymer,poly(arylether), porous polymer, or a combination thereof. Thesilsesquioxnane is, for instance, hydrogen silsesquioxnane (HSQ), methylsilsesquioxane (MSQ), or hybrido-organosiloxane polymer (HOSP). Thearomatic hydrocarbon is, for instance, SiLK. The organosilicate glassis, for instance, carbon black (e.g., black diamond, BD), 3MS, or 4MS.The fluorinated polymer is, for instance, PFCB, CYTOP, or Teflon. Thepoly(arylether) is, for instance, PAE-2 or FLARE. The porous polymer is,for instance, XLK, nanofoam, Awrogel, or Coral. The forming method ofthe dielectric layer 104 is, for instance, atomic layer deposition(ALD), chemical vapor deposition (CVD), spin coating (SOG), or acombination thereof. The wires 106 include a conductive layer and/or avia, and the material thereof can be a conductive material. Forinstance, the conductive material can be metal, metal alloy, metalnitride, metal silicide, or a combination thereof. In some exemplaryembodiments, the metal and metal alloy are, for instance, Cu, Al, Ti,Ta, W, Pt, Cr, Mo, or an alloy thereof. The metal nitride is, forinstance, titanium nitride, tungsten nitride, tantalum nitride, tantalumsilicon nitride (TaSiN), titanium silicon nitride (TiSiN), tungstensilicon nitride (WSiN), or a combination thereof. The metal silicide is,for instance, tungsten silicide, titanium silicide, cobalt silicide,zirconium silicide, platinum silicide, molybdenum silicide, coppersilicide, nickel silicide, or a combination thereof. In someembodiments, the forming method of the wires 106 can be a singledamascene process, a dual damascene process, or a combination thereof.The wires 106 electrically connect a(n) active device/passive device toa subsequent contact conductor 112 and/or pad 110.

A contact conductor 112 is disposed in the substrate material layer 102.The material of the contact conductor 112 can be a conductive material.For instance, the conductive material is metal alloy, metal nitride,metal silicide, or a combination thereof. In some exemplary embodiments,the metal and metal alloy are, for instance, Cu, Al, Ti, Ta, W, Pt, Cr,Mo, or an alloy thereof. The metal nitride is, for instance, titaniumnitride, tungsten nitride, tantalum nitride, tantalum silicon nitride(TaSiN), titanium silicon nitride (TiSiN), tungsten silicon nitride(WSiN), or a combination thereof. The metal silicide is, for instance,tungsten silicide, titanium silicide, cobalt silicide, zirconiumsilicide, platinum silicide, molybdenum silicide, copper silicide,nickel silicide, or a combination thereof. In some embodiments, thecontact conductor 112 is a through-silicon via (TSV), and based on theforming order, the forming method thereof can be substantially dividedinto a via-first process, a via-middle process, and a via-last process.For instance, in the via-first process, the contact conductor 112 isformed in the substrate material layer 102 before the front-end-of-line(FEOL) process of the wafer; in the via-last process, the contactconductor 112 is formed in the substrate material layer 102 after theback-end-of-the-line (BEOL) process of the wafer; and in the via-middleprocess, the contact conductor 112 is formed in the substrate materiallayer 102 between the FEOL and BEOL processes (i.e.,middle-end-of-the-line (MEOL) process). In the present embodiment, thecontact conductor 112 is formed in the substrate material layer 102 viaa via-middle process and electrically insulated from the substratematerial layer 102 via a dielectric material (not shown in figures), butthe invention is not limited thereto, and the contact conductor 112 canalso be formed in the substrate material layer 102 via a via-firstprocess or a via-last process.

The pad 110 is formed on the interconnect structure 108. The material ofthe pad 110 can be a conductive material. For instance, the conductivematerial is, for instance, the metal, metal alloy, metal nitride, metalsilicide, or a combination thereof as for contact conductor 112described above. The forming method of the pad 110 is, for instance, ametal patterning process or a metal damascene process.

The dielectric layer 114 is formed on the interconnect structure 108 andexposes the pad 110. The material of the dielectric layer 114 can be thedielectric material as for the dielectric layer 104 described above. Insome embodiments, the forming method of the dielectric layer 114 caninclude first forming a dielectric material layer (not shown) coveringthe pad 110 on the interconnect structure 108. Next, a portion of thedielectric material layer located on the pad 110 is removed to form thedielectric layer 114 exposing the pad 110. Alternatively, the formingmethod of the dielectric layer 114 can include first forming adielectric material layer (not shown) on the interconnect structure 108,then removing the portion of the dielectric material layer where the pad110 to be formed, and then forming the pad 110. In some embodiments, thedielectric material layer located on the pad 110 can be removed using aplanarization process. The planarization process is, for instance, achemical-mechanical polishing (CMP) process.

Referring further to FIG. 1A, a carrier plate 10 is provided. In someembodiments, the carrier plate 10 can be a carrier wafer similar to thewafer 100. In other words, the carrier plate 10 can also include aplurality of dies, and FIG. 1A shows one of the dies 11 (i.e., thirddie). The die 11 includes a substrate material layer 12, an interconnectstructure 18 (including a dielectric layer 14 and wires 16), a pad 20,and a dielectric layer 22, and the relative positions, materials, andforming methods thereof are respectively as provided for the substratematerial layer 102, the interconnect structure 108, the pad 110, and thedielectric layer 114 of the die 101 and are not repeated herein. In someembodiments, in the carrier plate 10 (carrier wafer), a contactconductor does not need to be formed in the substrate material layer 12,but the invention is not limited thereto.

Referring to both FIG. 1A and FIG. 1B, the carrier plate 10 is coveredby the wafer 100. In some embodiments, the carrier plate 10 can be acarrier wafer similar to the wafer 100, wherein the pad 110 of the die101 faces the carrier plate 10 and is connected to the pad 20 of the die11 of the carrier plate 10 (i.e., carrier wafer). As a result, since thecarrier plate 10 is a wafer, the carrier plate 10 does not need to beremoved in a subsequent process (a regular carrier plate for carrying awafer does not have an active device and/or an interconnect structure,and is therefore removed in a subsequent process), and therefore notonly can process be simplified and the cost of the carrier beeliminated, stacking density of the chip can be further increased. Insome embodiments, the pad 110 of the die 101 can be connected to the pad20 of the die 11 in the carrier plate 10 (i.e., carrier wafer) and thedielectric layer 114 of the die 101 can be connected to the dielectriclayer 22 of the carrier plate 10 using a hybrid bond (HB) method.

Referring to both FIG. 1B and FIG. 1C, a portion of the substratematerial layer 102 is removed to form a substrate 102 a, wherein thecontact conductor 112 is exposed on and protruded from a second surfaceS2 of the substrate 102 a. In some embodiments, the method of removing aportion of the substrate material layer 102 includes, in order,performing a thinning process and an etching process on the surface(i.e., back of the die 101) of the substrate material layer 102 awayfrom the interconnect structure 108 such that the contact conductor 112is exposed on and protruded from the second surface S2 of the substrate102 a. The thinning process includes, for instance, performing agrinding process on the surface of the substrate material layer 102 awayfrom the interconnect structure 108. The etching process is, forinstance, dry etching, wet etching, or a combination thereof. In someembodiments, the contact conductor 112 does not cover the surface (i.e.,the second surface S2) of the substrate 102 a away from the interconnectstructure 108. Moreover, the thickness of the substrate 102 a is lessthan the thicknesses of the substrate material layers 12 and 102. Insome embodiments, the substrate 102 a has a thickness t1, and 3μm<t1<100 μm; and the substrate material layers 12 and 102 have athickness t2, and t2 is about 775 μm. In other words, in the embodimentin which the carrier plate 10 is a carrier wafer, the thickness of thesubstrate material layer 12 thereof is greater than the thickness of thesubstrate 102 a (i.e., the thickness of the carrier wafer (thickness ofthe die 11) is greater than the thickness of the die 101 a), andtherefore when the die 101 a is carried thereon, the issue of difficultsubsequent process thereon due to an insufficient thickness of the die101 a can still be prevented.

Referring to FIG. 1D, a dielectric layer 116 is formed on the secondsurface S2 of the substrate 102 a, wherein the dielectric layer 116exposes the first contact conductor 112. The material of the dielectriclayer 116 is, for instance, a dielectric material. The dielectricmaterial is, for instance, silicon oxide, tetraethoxysiloxane (TEOS)silicon oxide, undoped silica glass (USG), or a combination thereof. Insome embodiments, the forming method of the dielectric layer 116includes first forming a dielectric material layer (not shown) coveringthe contact conductor 112 on the second surface S2 of the substrate 102a. Next, a portion of the dielectric material layer located on thecontact conductor 112 is removed to form a dielectric layer 116 exposingthe contact conductor 112. The forming method of the dielectric materiallayer is, for instance, ALD, CVD, SOG, or a combination thereof. Themethod of removing the dielectric material layer located on the contactconductor 112 can be a planarization process such as CMP. In someembodiments, the top surface of the dielectric layer 116 and the topsurface of the contact conductor 112 are coplanar, and the dielectriclayer 116 surrounds the contact conductor 112 protruded from the secondsurface S2.

Referring to FIG. 1E, a wafer 200 is provided. The wafer 200 includes aplurality of dies, and FIG. 1E only shows one of the dies 201 (i.e.,second die). The die 201 includes a substrate material layer 202, aninterconnect structure 208 (including a dielectric layer 204 and wires206), a pad 210, a contact conductor 212, and a dielectric layer 214. Insome embodiments, the wafer 200 is similar to the wafer 100, andtherefore the relative positions, materials, and forming methods of thesubstrate material layer 202, the interconnect structure 208, the pad210, the contact conductor 212, and the dielectric layer 214 in the die201 thereof are substantially similar to those of the substrate materiallayer 102, the interconnect structure 108, the pad 110, the contactconductor 112, and the dielectric layer 114 of the die 101 and are notrepeated herein.

Next, the wafer 200 covers the wafer 100 a such that the die 201 isdocked with the die 101 a, and the contact conductor 112 of the die 101a is directly physically in contact with the pad 210 of the die 201. Asa result, another pad for connecting the contact conductor 112 and thepad 210 does not need to be formed on the dielectric layer 116, suchthat the process can be simplified and the process yield of thechip-stack structure can be increased and production cost thereof can bereduced as a result. In some embodiments, the contact conductor 112 ofthe die 101 a can be directly physically connected to the pad 210 of thedie 201 using a hybrid bonding method. In some embodiments, the contactconductor 112 has a width A; the pad 210 has a width B, and 5≤B/A, inparticular 5≤B/A≤10, or even B/A>10. As a result, even if misalignmentoccurs to the contact conductor 112 and the pad 210, the contactconductor 112 can still be electrically connected to the pad 210 wellwithout affecting other adjacent contact conductors 112 and/or pads 210(for instance, being too close to the adjacent contact conductor 112and/or the pad 210 results in a risk from an electron migration (EM)effect, such that a risk of short circuit is present). In the presentembodiment, the active surface of the die 201 faces the back of the die101 a, that is, in the present embodiment, a back-to-front stackingmethod is exemplified, but the invention is not limited thereto. In someembodiments, a front-to-front or back-to-back stacking method can alsobe used. Moreover, referring to FIG. 1A and FIG. 1E, in the presentembodiment, two wafers (wafers 100 and 200) are stacked on the carrierplate 10 as an example, but the invention is not limited thereto, andthe process of, for instance, FIG. 1C to FIG. 1E, can be furtherperformed on the wafer 200 to form a wafer 200 a and stack one or aplurality of wafers thereon.

Referring to both FIG. 1E and FIG. 2, in the present embodiment, twowafers are stacked on the carrier plate 10 as an example, and therefore,the die 201 is the top-most die of the die-stack structure, but theinvention is not limited thereto. The process of, for instance, FIG. 1Cto FIG. 1D is performed on the die 201 to form a die 201 a, and thecontact conductor 212 thereof is exposed on and protruded from thesurface of the substrate 202 a away from the interconnect structure 208,and the dielectric layer 216 is formed on the surface of the substrate102 a away from the interconnect structure 208 and exposes the contactconductor 212. In an embodiment, the material and the forming method ofthe dielectric layer 216 are substantially similar to those of thedielectric layer 116 and are not repeated herein. Next, a redistributionlayer (RDL) 218 is formed on the dielectric layer 216 to define the padof the top-most die of a die-stack structure 300. The redistributionlayer 218 is electrically connected to the corresponding contactconductor 212. The material of the redistribution layer 218 can be theconductive material as for the contact conductor 112 set forth above.For instance, the conductive material can be the metal, metal alloy,metal nitride, metal silicide, or a combination thereof.

Referring to FIG. 3, a singulation process is performed on the die-stackstructure 300 to cut the die-stack structure 300 into a plurality ofchip-stack structures 300 a separated from one another. In thefollowing, the chip-stack structure 300 a of the present embodiment isdescribed via FIG. 3. Moreover, although the manufacturing method of thechip-stack structure 300 a of the present embodiment is exemplified bythe manufacturing method above, the manufacturing method of thechip-stack structure 300 a of the invention is not limited thereto.

Referring to FIG. 3, the chip-stack structure 300 a includes a chip 101b (i.e., first chip) and a chip 201 b (i.e., second chip). The chip 101b and the chip 201 b respectively correspond to the die 101 a and thedie 201 a (as shown in FIG. 2). The chip 201 b is located on the chip101 b. The chip 101 b includes a substrate 102 a (first substrate), aninterconnect structure 108 (first interconnect structure), a pad 110(first pad), a contact conductor 112 (first contact conductor), and adielectric layer 114. The interconnect structure 108 is located on afirst surface S1 of the substrate 102 a. The pad 110 is located on theinterconnect structure 108. The contact conductor 112 is located in thesubstrate 102 a and exposed on a second surface S2 of the substrate 102a opposite to the first surface S1. The chip 201 b includes a substrate202 a (second substrate), an interconnect structure 208 (secondinterconnect structure), a pad 210 (second pad), a contact conductor 212(second contact conductor), and a dielectric layer 214. The interconnectstructure 208 is located on the substrate 202 a. The pad 210 is locatedon the interconnect structure 208. The contact conductor 212 is locatedin the substrate 202 a, wherein the contact conductor 112 of the chip101 b is directly physically in contact with the pad 210 of the chip 201b. The contact conductor 112 has a width A, the pad 210 has a width B,and 5≤B/A, such as 5≤B/A≤10, or even B/A>10. Moreover, the contactconductor 112 does not cover the second surface S2 of the substrate 102a. In some embodiments, the chip-stack structure 300 a further includesa carrier plate 10 located below the chip 101 b. In some embodiments,the carrier plate 10 is a carrier chip. The pad 110 of the chip 101 b isconnected to the pad 20 of the carrier plate 10 (i.e., the carrierchip), wherein the thickness of the carrier chip is greater than thethickness of the chip 101 b. In some embodiments, the chip-stackstructure 300 a further includes a dielectric layer 116 located betweenthe chip 101 b and the chip 201 b. In some embodiments, the activesurface of the chip 201 b faces the back of the chip 101 b.

Based on the above, in the chip-stack structure and the manufacturingmethod thereof of the embodiments, since the first contact conductor ofthe first chip is directly physically in contact with the second pad ofthe second chip, a pad for connecting the first contact conductor andthe second pad does not need to be formed on the second surface of thefirst substrate, such that the process can be simplified, and theprocess yield of the chip-stack structure can be increased andproduction cost thereof can be reduced.

Although the invention has been described with reference to the aboveembodiments, it will be apparent to one of ordinary skill in the artthat modifications to the described embodiments may be made withoutdeparting from the spirit of the invention. Accordingly, the scope ofthe invention is defined by the attached claims not by the abovedetailed descriptions.

What is claimed is:
 1. A chip-stack structure, comprising: a first chipcomprising: a first substrate having a first surface and a secondsurface opposite to the first surface; a first interconnect structurelocated on the first surface of the first substrate; and a first contactconductor located in the first substrate and exposed on the secondsurface of the first substrate; a second chip located on the first chipand comprising: a second substrate; a second interconnect structurelocated on the second substrate; and a second pad located on the secondinterconnect structure; a first dielectric layer located on the secondsurface of the first substrate; and a redistribution layer is formed onthe second chip, wherein the first contact conductor is directlyphysically in contact with the second pad, the first contact conductorhas a width A, the second pad has a width B, and 5≤B/A.
 2. Thechip-stack structure of claim 1, further comprising a first pad locatedon the first interconnect structure.
 3. The chip-stack structure ofclaim 2, wherein the first contact conductor does not directlyphysically in contact with the first pad.
 4. The chip-stack structure ofclaim 1, further comprising a second contact conductor located in thesecond substrate and electrically connected with the redistributionlayer.
 5. The chip-stack structure of claim 1, wherein the secondcontact conductor does not physically directly in contact with thesecond pad.
 6. The chip-stack structure of claim 1, further comprising asecond dielectric layer located between the redistribution layer and thesecond chip.
 7. The chip-stack structure of claim 6, wherein the secondcontact conductor is exposed on the second dielectric layer.
 8. Thechip-stack structure of claim 2, further comprising a carrier platelocated below the first chip, and the carrier plate comprises aplurality of dies.
 9. The chip-stack structure of claim 8, wherein athickness of the plurality of dies of the carrier plate is greater thana thickness of the first chip.
 10. The chip-stack structure of claim 2,further comprises a carrier plate which is a carrier chip, and the firstpad of the first chip is connected to a pad of the carrier chip.
 11. Thechip-stack structure of claim 1, wherein the first contact conductor isa through-silicon via.
 12. The chip-stack structure of claim 1, whereinthe first contact conductor does not cover the second surface of thefirst substrate.
 13. The chip-stack structure of claim 1, wherein a topsurface of the first dielectric layer is coplanar with a top surface ofthe first contact conductor.
 14. The chip-stack structure of claim 1,wherein a portion of the first dielectric layer is directly physicallyin contact with the second pad.
 15. A chip-stack structure, comprising:a first chip comprising: a first substrate having a first surface and asecond surface opposite to the first surface; a first interconnectstructure located on the first surface of the first substrate; a firstpad located on the first interconnect structure; and a first contactconductor located in the first substrate and exposed on the secondsurface of the first substrate; a second chip located on the first chipand comprising: a second substrate; a second interconnect structurelocated on the second substrate; a second pad located on the secondinterconnect structure; and a second contact conductor located in thesecond substrate; a first dielectric layer located between first chipand second chip; and a redistribution layer is formed on andelectrically connected to the second contact conductor, wherein thefirst contact conductor is directly physically in contact with thesecond pad, the first contact conductor has a width A, the second padhas a width B, and 5≤B/A.
 16. The chip-stack structure of claim 15,wherein the first contact conductor does not directly physically incontact with the first pad.
 17. The chip-stack structure of claim 15,wherein the second contact conductor does not physically directly incontact with the second pad.
 18. The chip-stack structure of claim 15,wherein the first contact conductor is a through-silicon via.
 19. Thechip-stack structure of claim 15, further comprising a second dielectriclayer located between the redistribution layer and the second chip. 20.The chip-stack structure of claim 19 wherein the second contactconductor is exposed on the second dielectric layer.
 21. The chip-stackstructure of claim 15, further comprising a carrier plate located belowthe first chip, and the carrier plate comprises a plurality of dies. 22.The chip-stack structure of claim 21, wherein a thickness of theplurality of dies of the carrier plate is greater than a thickness ofthe first chip.
 23. The chip-stack structure of claim 15, furthercomprises a carrier plate which is a carrier chip, and the first pad ofthe first chip is connected to a pad of the carrier chip.
 24. Thechip-stack structure of claim 15, wherein the first contact conductordoes not cover the second surface of the first substrate.
 25. Thechip-stack structure of claim 15, wherein a top surface of the firstdielectric layer is coplanar with a top surface of the first contactconductor.
 26. The chip-stack structure of claim 15, wherein a portionof the first dielectric layer is directly physically in contact with thesecond pad.